Xilinx Field Programmable Gate Array, Part #: XC9572XL-7CS48I| FPGA | DEX test DKx#) • On-die DLL generates

DKx#) • On-die DLL generates CK edge-aligned data and output data clock signals • Data valid signal (QVLD) • 32ms refresh (16K refresh for each bank

IPS (Intelligent Power Switch) MOSFET

making them excellent replacements for low-voltage Zener diodes in many applications

Data rate: 14 Gb/s

Palm & finger textured

Xilinx Field Programmable Gate Array, Part #: XC9572XL-7CS48I| FPGA | DEX test DKx#) • On-die DLL generatesXilinx FPGA XC9572XL 7CS48IFeatures 5 ns pin to pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages 44 pin PLCC (34 user I O pins) 44 pin VQFP (34 user I O pins) 48 pin CSP (38 user I O pins) 64 pin VQFP (52 user I O pins) 100 pin TQFP (72 user I O pins) Pb free available for all packages Optimized for high performance 3. 3V systems Low power operation 5V tolerant I O pins accept